Analog and digital circuits are both present in some system chips. Signals may cross from the digital domain to the analog domain, and vice-versa. Analog signals may be converted to digital for complex digital processing, such as by a Digital Signal Processor (DSP).
Many types of Analog-to-Digital Converters (ADC's) have been used for a wide variety of applications. Flash ADC's compare analog signal voltages to multiple voltage levels in an instant to produce a multi-bit digital word that represents the analog voltage. Successive-approximation ADC's use a series of stages to convert an analog voltage to digital bits. Each stage compares an analog voltage to a reference voltage, producing one digital bit. In sub-ranging ADC's, each stage compares an analog voltage to several voltage levels, so that each stage produces several bits. Succeeding stages generate lower-significant digital bits than do earlier stages in the pipeline.
Algorithmic, re-circulating, or recycling ADC's use a loop to convert an analog voltage. The analog voltage is sampled and compared to produce a most-significant digital bit. Then the digital bit is converted back to analog and subtracted from the analog voltage to produce a residue voltage. The residue voltage is then multiplied by two and looped back to the comparator to generate the next digital bit. Thus the digital bits are generated over multiple cycles in the same comparator stage.
FIG. 1 shows a Successive-Approximation-Register ADC. Successive-Approximation-Register SAR 102 receives a clock CLK and contains a register value that is changed to gradually zero-in on a close approximation of the analog input voltage VIN. For example, the value in SAR 102 may first be 0.5, then 0.25, then 0.375, then 0.312, then 0.281, then 0.296, then 0.304, then 0.308, then 0.31, then 0.311, and finally 0.312 when comparing to a VIN of 0.312 volts. SAR 102 outputs the current register value to digital-to-analog converter (DAC) 100, which receives a reference voltage VREF and converts the register value to an analog voltage VA.
The input analog voltage VIN is applied to sample-and-hold circuit 104, which samples and holds the value of VIN. For example, a capacitor can be charged by VIN and then the capacitor isolated from VIN to hold the analog voltage. The sampled input voltage from sample-and-hold circuit 104 is applied to the inverting input of comparator 106. The converted analog voltage VA is applied to the non-inverting input of comparator 106.
Comparator 106 compares the converted analog voltage VA to the sampled input voltage and generates a high output when the converted analog voltage VA is above the sampled VIN, and the register value in SAR 102 is too high. The register value in SAR 102 can then be reduced.
When the converted analog voltage VA is below the sampled input voltage, comparator 106 generates a low output to SAR 102. The register value in SAR 102 is too low. The register value in SAR 102 can then be increased for the next cycle.
The register value from SAR 102 is a binary value of N bits, with D(N−1) being the most-significant-bit (MSB) and D0 being the least-significant-bit (LSB). SAR 102 can first set the MSB D(N−1), then compare the converted analog voltage VA to the input voltage VIN, then adjust the MSB and/or set the next MSB D(N−2) based on the comparison. The set and compare cycle repeats until after N cycles the LSB is set. After the last cycle, the end-of-cycle EOC signal is activated to signal completion. A state machine or other controller can be used with or included inside SAR 102 to control sequencing.
DAC 100 or sample-and-hold circuit 104 may have an array of capacitors. The capacitors have binary-weighted values, such as 1, 2, 4, 8, 16, 32, . . . times a minimum capacitor size. For example, a 6-bit DAC may have an array of capacitors of 1, 2, 4, 8, 16, 32 times a minimum capacitance C. Higher-resolution DAC's such as a 11-bit DAC have much larger capacitor values, such as 2N-1=1024.
FIG. 2 is a graph showing a SAR ADC resolving an input voltage. The register value in SAR 102 is initially set to one-half, or 10000. Comparator 106 determines that the input voltage VIN is less than the converted value from SAR 102, so in the next iteration SAR 102 is set to one-quarter, or 01000. Comparator 106 determines that the input voltage VIN is greater than the converted value from SAR 102, so in the third iteration SAR 102 is set to three-eighths, or 01100. Comparator 106 determines that the input voltage VIN is less than the converted value from SAR 102 in the third iteration, so in the fourth iteration SAR 102 is set to five-sixteenths, or 01010. Now comparator 106 determines that the input voltage VIN is greater than the converted value from SAR 102, so in the fifth iteration SAR 102 is set to 9/32, or 01011. The final comparison is that VIN is above the converted value, so the final result is 01011.
While such capacitor-array DAC's are useful, the large size of the MSB capacitors requires a large amount of charge to be transferred. The minimum capacitor size C can be shrunk to reduce the overall capacitance of the capacitor array and thus reduce the dynamic power requirements. The minimum capacitor size may be restricted by the process technology. For example, a sub-micron process may allow for a 4×4 μm2 minimum physical-size for a metal-to-metal capacitor, which has a capacitance of about 16 fF.
Matching capacitor values in the binary-weighted array is very important for obtaining precise results. Inherent device and impedance mismatches in deep sub-micron processes limit converter resolutions to about 10 bits.
Resolution can be increased through calibration. Before the input voltage is converted to a digital value, a sequence of steps known as calibration can be performed. Calibration measures each capacitor's mismatches by charge sharing with an additional array of capacitors. Capacitors in the additional array are connected and disconnected until a voltage match occurs. A mis-match value is obtained by recording the enable signals for the capacitors once the final voltage match occurs.
The procedure is then repeated for the next capacitor in the main array, and its mis-match value stored. Once the calibration procedure has operated upon all capacitors in the main array, the mis-match values are saved for each of the capacitors as capacitor coefficients. These capacitor coefficients can then program the second array to subtract out the mis-match errors as the analog input voltage VIN is processed. As successively smaller capacitors are evaluated in the main array, their saved capacitor coefficients are applied to the second capacitor array.
In the example of FIG. 2, when the MSB D4 is converted, the MSB capacitor is switched to receive the shared charge and lower-significance capacitors are switched off or isolated. The error for the MSB capacitor was previously determined by calibration as 10000, and this calibration value of 10000 is applied to the second (calibration) array of the DAC to compensate for the MSB capacitor's error in the main array. The value of the MSB is determined to be 0. Then the penultimate MSB capacitor is switched to share charge in the main DAC, but the MSB capacitor is isolated in the main array since the MSB's digital value was determined to be zero (D4=0). The error for the penultimate MSB was determined to be 01000 during calibration, and the calibration value of 01000 is applied to the second (calibration) array to compensate. The comparator determines that the penultimate MSB D3=1.
In the next cycle, the MSB capacitor is isolated but the MSB-1 and MSB-2 capacitors are connected to share charge in the main array. The calibration values for both the MSB-1 and MSB-2 capacitors are read and added together to get the compensation value of 01100 that is applied to the second array to compensate for the errors of both the MSB-1 and MSB-2 capacitors. The comparator determines that the MSB-2 digital value D2=0.
In the fourth cycle, the MSB capacitor and the MSB-2 capacitors are isolated but the MSB-1 and MSB-3 capacitors are connected to share charge in the main array. The calibration values for both the MSB-1 and MSB-3 capacitors are read and added together to get the compensation value of 01010 that is applied to the second array to compensate for the errors of both the MSB-1 and MSB-3 capacitors. The comparator determines that the MSB-3 digital value D1=1.
In the final cycle, the MSB capacitor and the MSB-2 capacitors are isolated but the MSB-1 and MSB-3 and LSB capacitors (D3, D1, D0) are connected to share charge in the main array. The calibration values for the MSB-1 and MSB-3 and LSB capacitors (D3, D1, D0) are read and added together to get the compensation value of 01011 that is applied to the second array to compensate for the errors of the connected capacitors D3, D1, D0. The comparator determines that the LSB digital value is D0=1. Thus the final result is that the digital value 01011 represents the analog input voltage.
FIG. 3 is a diagram of a SAR ADC with binary-weighted capacitor arrays and a calibration sub-DAC capacitor array. Binary-weighted X-side capacitor array 40 has capacitors 22-28 that connect to node VX that carries voltage VX to the inverting input of comparator 20.
The non-inverting input of comparator 20 connects to the Y-side capacitor array, which is used for calibration and compensation of errors in capacitors 22-28 in binary-weighted X-side capacitor array 40.
Binary-weighted calibration Y-side capacitor array 42 has capacitors 52-58 that connect to node VY that carries voltage VY to the non-inverting input of comparator 20. A calibration value Y5:Y0,YT is applied to switches 68-62. YT is the termination bit.
The resolution of the ADC is one less than the number of binary bits stored in Successive-Approximation-Register (SAR) 206. SAR 206 stores termination bit XT in addition to binary bits X5:X0. SAR 206 also stores the calibration Y-side bits Y5:Y0, YT.
Before a differential analog input voltage VINP, VINN, is converted to a digital value, a calibration procedure is performed. The calibration procedure first finds the mis-match errors for each of capacitors 28-22 in binary-weighted X-side capacitor array 40 and stores the error coefficients for each of the X-side capacitors. Then the calibration process may be reversed and performed on capacitors 58-52 in binary-weighted calibration Y-side capacitor array 42, and the resulting Y-side error coefficients stored for each of the Y-side capacitors.
Once calibration is completed, normal operation occurs in which analog voltages are converted to digital values. The error coefficients are used to successively program switches 68-62 in calibration Y-side capacitor array 42 to subtract the mis-match errors as each of X-side capacitors 28-23 are evaluated.
During normal operation, binary-weighted X-side capacitor array 40 has switches 32-38 that switch input voltage VINP to the bottom plate of capacitors 22-28 during a VIN sampling phase S1, and switch bits X5:X0, XT from SAR 206 during a conversion phase. Grounding switch 112 closes during sampling phase S1 and is open during the conversion phase. The top plates of capacitors 22-28 are connected to the inverting input of comparator 20 and generate voltage VX.
Capacitors 22-28 increase in binary weights or multiples of the minimum capacitor size C/64, with capacitance C/64 for termination capacitor 22 and capacitor 23, capacitance C/32 for capacitor 24, and capacitance of C/8 for capacitor 26. Capacitors 28, 27 have capacitances of C/2 and C/4. The capacitor size and arrangement in binary-weighted X-side capacitor array 40 on the X-side is matched by that in binary-weighted Y-side capacitor array 42.
The X-side bits X5:X0, XT from SAR 206 are applied to the bottom plates of capacitors 22-28 in binary-weighted X-side capacitor array 40 during the conversion phase. The bottom plates are connected to Vinp during the sampling phase S1 of normal operation. Control logic 204 can generate control signals such as S1 and adjust values in SAR 206 in response to compare results from comparator 20. Once all bits in SAR 206 have been adjusted, a busy signal can be negated to indicate that conversion is complete.
Binary-weighted Y-side capacitor array 42 has switches 62-68 that switch input voltage VINN to the bottom plate of capacitors 62-68 during a first sampling phase, and switch bits Y5:Y0, YT from SAR 206 during a conversion phase of normal operation. Grounding switch 114 closes during sampling phase S1 and is open during the conversion phase. The top plates of capacitors 52-58 are connected to the inverting input of comparator 20 and generate voltage VY.
During normal operation, a differential analog input voltage is applied to inputs VINP, VINN. If a single-ended analog voltage were used, it could be applied to VINP and a fixed voltage such as ground or VDD/2 could be applied to VINN. Binary-weighted X-side capacitor array 40 can act as sample-and-hold circuit while binary-weighted Y-side capacitor array 42 acts as DAC 100 of FIG. 1.
FIG. 4A shows a prior-art timing of operation of the DAC of FIG. 3. Calibration values are stored for each of capacitors 22-28 of FIG. 3 during a calibration procedure. During conversion of an analog voltage to a digital value, a top-down procedure is used. The MSB is tested first by charge sharing with the MSB capacitor 28, while a calibration value Y5:Y0 for this MSB capacitor is applied to capacitors 62-68 in calibration Y-side capacitor array 42. Then successively smaller digital bits are tested using smaller capacitor in binary-weighted X-side capacitor array 40. The calibration value applied to calibration Y-side capacitor array 42 at each step depends on which of capacitors 62-68 is connected to share charge with line VX during that cycle, which depends on the bit being tested, and the results of earlier (higher-significant bits) tested earlier. Thus the compensation value at each step must be calculated and depends on the earlier results.
The calibration values applied to calibration Y-side capacitor array 42 are know as the compensation value, since it is a sum of calibration values for the currently connected capacitors in binary-weighted X-side capacitor array 40.
In FIG. 4A, bit N+1 is being converted from analog to a digital value, then bit N, and then bit N−1. A conversion-cycle clock CLK times synchronizes conversions.
At the beginning of each bit's cycle, the conversion value is calculated during time period 120. The calibration values for the capacitors in binary-weighted X-side capacitor array 40 that are connected are read and summed to get the conversion value during time period 120. Then the calculated conversion value is applied to the capacitors in calibration Y-side capacitor array 42, such as by switching voltages to these capacitors, during time period 12. Then charge sharing occurs and the voltages applied to comparator 20 change. The comparator output eventually settles to a stable result during time period 124. The comparator result is analyzed to determine the digital value for bit N+1.
Once this digital value for bit N+1 is known, then the capacitors in binary-weighted X-side capacitor array 40 can be switched to test the next bit N. The compensation value for bit N cannot be determined until the result for bit N+1 is known, which occurs after the comparator has settled during time period 124.
When a higher frequency is used for cycle clock CLK, such as 1 GHz, the time available for calculations and analog comparison is reduced. FIG. 4B shows reduced timing at higher conversion frequencies. The compensation values CAL_CAP are not available until calculations are completed in time period 120. The higher frequency of CLK means that these calculations occupy a larger portion of time, and time period 120 is stretched. There may be less available time period 12 for applying these compensation values to calibration Y-side capacitor array 42. Analog comparison also takes relatively more time period 124. There may be insufficient remaining time 14 for the compare result to be analyzed and the set-up times before the next rising edge of CLK to be met for logic to be met within the circuits. Thus higher-frequency operation may not be possible due to the relatively long times to read calibration values and calculate compensation values for each bit's cycle during conversion.
What is desired is an ADC with a calibration DAC to measure capacitor mis-match errors. A SAR ADC with more efficient generation of conversion values from stored calibration values is desired to allow for higher-speed operation. A calibration ADC that operates at high frequencies is desired.